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Intel is about to launch the Gen 11 core display architecture, the performance is more than twice the previous generation

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 According to foreign media reports, at the GDC Game Developers Conference in March, Intel (intel) will introduce their new Gen 11 core display architecture. And this architecture is expected to be used in the 10-nanometer Ice Lake processor launched at the end of 2019. The floating point performance is said to be as high as 1TFLOPS or more, which will be twice that of the previous generation. According to the report, the Intel graphics team recently announced some new features displayed in the Gen11 core, emphasizing that the architecture is both efficient and performance. Moreover, the core area of ​​the computing unit is smaller than that of Gen 9, and the area under the same process is only 75% of that of Gen 9, which not only improves performance, but also increases battery life. In fact, at the 2018 Architecture Day event, Intel has announced their GPU roadmap. From Skylake to the current Coffee Lake Refresh processor, the core display of the 4th generation processor is still based on the Gen9 architecture. As for the Gen10 architecture, it was originally used on the 10nm Cannonlake processor, but now it has directly entered the Gen11 GPU era, and then it will be the newly developed Gen12 architecture, which will also derive Intel’s independent Display GPU. This time, Intel’s announcement of the new features of the Gen11 architecture pointed out that Intel has reduced the computing unit displayed in the Gen11 core, emphasizing that its Gen11 core display emphasizes both performance and performance, and also supports more advanced 3D and multimedia display functions. Enable users to have a better gaming experience. According to the report, some market participants said that even under the same process technology, Intel’s Gen11 core display is only 75% of Gen9’s core area, which means that the area is reduced by a quarter, but the Gen11 core display is still 10. It is built by the nano process, which shows that the dual improvements in its architecture and process should allow the core area displayed in the Gen11 core to be greatly reduced, and finally more ALU computing units can be squeezed into.

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